Abstract
Superconducting logic is fast and energy efficient relative to CMOS but also fundamental studies are needed to scale up circuits for greater utility. Recently, ballistic shift registers for single-flux quanta (SFQ) bits have been shown in simulations to allow high-efficiency superconducting gates. However, these gates are unpowered, such that the bits slow after each gate operation and thus only a short sequence of gates is possible without added power. Here, we theoretically show that a circuit based on an Aharonov-Casher ring can power these shift registers by boosting the bit velocity to a constant value, despite their unusual bit states constituted by two polarities of SFQ. Each bit state is forced into a different ring arm and then accelerated as part of the operation. The circuit dynamics depend on various circuit parameters and choices of how to merge the bit-state paths. One design from each merge design choice is proposed to possibly enable scaling up to an array of gates by adding serial biasing in a relatively simple way. We find adequate performance for ballistic logic in terms of boosted velocity, energy efficiency, and parameter margins. We also discuss the classical barriers of the circuit, which relate to the Aharonov-Casher effect in a different parameter regime.