|dc.description.abstract||This thesis describes a demonstration field programmable gate array (FPGA) based radio intended for high frequency applications. This prototype uses a Xilinx Spartan-3 FPGA to provide many signal processing functions previously executed in a microprocessor or DSP.
The FPGA radio described here has separate receive and transmit functions. Operating frequency and channel bandwidth are software configurable. System test frequency was 13.45 MHz corresponding to a University narrow band frequency shift keying licence.
The system uses three processes – radio frequency (RF), mixed signal devices (MSD) and FPGA computation. Several Xilinx IP cores are used integrated with Verilog code.
The receive path uses direct analogue to digital converter (ADC) signal acquisition using the FPGA system clock at 50 MHz. The transmit path uses a similar approach using a digital to analogue converter (DAC) at the same clock rate.
A number of technologies have been used in this implementation. These include direct digital synthesis (DDS), cascaded integrator comb (CIC) decimation, digital frequency down conversion (DDC) to and Q, complex frequency demodulation, software pulse width modulator DACs with 10 bit resolution and parameter tuned digital filters (PTDF).
The system has been successfully built and tested. Receive and transmit channels have behaved as predicted. It is shown that low cost, medium resolution mixed signal devices can achieve land mobile radio communication performance standards. From this, increased MSD bit resolution can be expected to exhibit even higher performance.||